Detailed Explanation of the Differences Between PCIe 5.0 and PCIe 6.0

Epigraph: From 32GT/s to 64GT/s, it may seem like just a doubling of speed, but behind it is a complete transformation of the technical route.

Introduction: More Than Just Doubling the Speed

After working in the AI server and data center industry for so many years, the question I’m most often asked is: What’s the real difference between PCIe 5.0 and 6.0? Isn’t it just doubling the speed?

Every time I hear this question, I have to break it down for everyone: The upgrade from PCIe 5.0 to 6.0 is much more dramatic than the previous generations. From 3.0 to 4.0 and 4.0 to 5.0, although the speed also doubled, the technical route remained basically the same—both used NRZ encoding and similar equalization architectures. But from 5.0 to 6.0, the entire technical foundation of the physical layer has been completely replaced.

To help everyone understand how thorough this upgrade is, I’ve put together a detailed comparison that’s easy to understand, no need to overthink it.

First, here’s a table of core parameter comparisons, so you can see the differences at a glance:

Next, I’ll break down what’s behind each of these differences one by one, using plain language throughout—no obscure jargon, so I guarantee everyone can understand it.

1. Encoding Method: A Fundamental Shift from NRZ to PAM4

This is the core difference between the two generations, and once you understand this, all other differences will be easy to grasp.

PCIe 5.0 and all previous versions use NRZ encoding, also known as Non-Return-to-Zero encoding, or PAM2 for short. Simply put, it sends 1 bit per unit interval (colloquially, "each short transmission time")—either 0 or 1. The signal eye diagram (which you can think of as a "clarity" diagram of the signal) is a big "eye," which is very intuitive.

PCIe 6.0, however, uses PAM4 encoding (Four-Level Pulse Amplitude Modulation) for the first time. Its advantage is that it can send 2 bits per unit interval, corresponding to four levels: 00, 01, 10, and 11. As a result, the signal eye diagram becomes three small "eyes" stacked together, which is equivalent to fitting twice as much information in the same amount of time.

Many people may ask: How can PAM4 double the speed without increasing the frequency?

It’s actually quite simple: The Nyquist frequency of PCIe 5.0 is 16GHz (half of 32GT/s). After PCIe 6.0 adopts PAM4, although the speed doubles to 64GT/s, the Nyquist frequency remains 16GHz—because it transmits 1 extra bit per unit interval. This means the fundamental frequency of the signal doesn’t change, so the frequency requirements for the printed circuit board (PCB) and connectors don’t increase significantly, and the transmission distance can be similar to that of 5.0, without the need to modify the hardware transmission design.

But there’s no free lunch—PAM4 also has its shortcomings, which we need to make clear:

1.  Degraded Signal Clarity: The overall voltage amplitude is fixed, and each of PAM4’s three "small eyes" is only one-third the height of NRZ’s "big eye." Theoretically, the signal clarity (signal-to-noise ratio) of PAM4 is about 9.5dB worse than that of NRZ, which simply means it’s more susceptible to interference.

2.  Weaker Anti-Interference Ability: Whether it’s power supply interference, crosstalk between signals, or signal reflection, all are more likely to cause bit errors (data transmission errors) in a PAM4 system.

3.  More Troublesome Testing: In the past, testing signals only required measuring one "big eye," but now we have to measure three "small eyes" and pay attention to new indicators like linearity (RLM), which significantly increases the difficulty and cost of testing.

2. Data Stream Structure: Flit Mode is Mandatory

PCIe 5.0 still uses the old method: 128b/130b encoding, which has an "overhead" of about 1.5% (meaning when transmitting data, you have to send a little extra irrelevant auxiliary content). It also supports TLP packets (data "packets" for transmission) of different sizes, a mode called "Non-Flit." Each "packet" has its own check (CRC), which is equivalent to an exclusive "anti-counterfeiting label" for each packet.

To match PAM4 encoding and the FEC error correction technology we’ll discuss later, PCIe 6.0 must enable Flit mode (simply put, fixed-size "data packets"). A Flit is a fixed-length data block—256 bytes—and its internal structure is clear, breaking down into:

- 235 bytes of TLP: The core data that actually needs to be transmitted

- 6 bytes of DLP: Equivalent to a "middle-layer label" for the data, responsible for link layer transmission connection

- 8 bytes of CRC: A check code used to verify if the data was transmitted correctly

- 6 bytes of FEC: "Backup data" for error correction, which we’ll explain in detail later

Many people may wonder: Why do we have to use fixed-size "packets"? The reasons are simple, just three points:

1.  Convenient for FEC Error Correction: FEC error correction is calculated in fixed-length blocks, and a Flit is exactly a complete processing unit—no need to split it, making it more efficient.

2.  Reduced Overhead: The old extra overheads like sync headers and framing tokens have been optimized out. Although the packets are fixed-size, the overall bandwidth utilization is actually improved.

3.  Easier Error Handling: First, FEC fixes small correctable errors on the spot, then CRC checks again. If it can’t be fixed, a retransmission is initiated. The process is clear and doesn’t involve back-and-forth trouble.

3. Bit Error Rate and Error Correction Mechanism: Newly Added FEC Error Correction Function

PCIe 5.0 has very strict requirements for data transmission errors: the end-to-end bit error rate (simply the probability of incorrect data transmission) must not exceed 1E-12, meaning at most 1 bit error for every 1 trillion bits transmitted. It relies on physical layer equalization technology plus link layer retransmission, with no dedicated error correction function.

Because PAM4 encoding is inherently more prone to bit errors, PCIe 6.0 specifically adds a lightweight forward error correction (FEC for short; colloquially, "error correction backup" carried during transmission). The specification also defines a new indicator called FBER (First Bit Error Rate), which requires ≤ 1E-6. Although this seems looser than 5.0’s requirement, with FEC assistance, the overall error correction capability is actually stronger.

How does FEC work? It’s simple: When sending data, 6 bytes of FEC redundant information (i.e., "backup data") are calculated for each Flit and sent along with it. After receiving, the receiver first uses FEC to fix small correctable errors on the spot. If the error is too large for FEC to fix, CRC detects it and initiates a retransmission.

The advantages of this two-step mechanism of "FEC first for error correction, then CRC for error verification" are particularly obvious:

- Most single-bit small errors can be fixed directly by FEC without retransmission, keeping latency under control and not slowing down the overall speed.

- The probability of retransmission is very low, controlled within 5E-6, and the additional bandwidth consumption is only about 0.05%, which barely affects normal use.

- Compared to Ethernet’s RS-FEC (latency of about 100 nanoseconds), PCIe 6.0’s lightweight FEC has much lower latency and won’t affect the normal operation of devices.

4. Receiver Equalization: Significant Upgrade in Error Correction Capability

During high-speed signal transmission, signals will attenuate—just like sound getting quieter the farther it travels. At this time, "equalization" technology is needed to compensate, allowing the receiver to clearly receive the signal. PCIe 5.0’s reference DFE (Decision Feedback Equalization, a type of error correction technology) has 3 taps, equivalent to only 3 "error correction assistants."

Because PAM4 signals are more susceptible to interference, PCIe 6.0 has higher requirements for error correction capability. The reference DFE jumps to 16 taps—equivalent to several times more "error correction assistants." The receiver’s digital signal processing capability is also greatly improved, better able to eliminate "tail interference" (the extra interference left after signal transmission).

In addition, CTLE (Continuous Time Linear Equalization) has also been upgraded, from 4 poles/2 zeros to 6 poles/3 zeros, with stronger ability to compensate for signal attenuation.

Many people may ask: Why do we need so many "error correction assistants" (taps)? Because PAM4’s three "small eyes" have different equalization requirements—especially the top and bottom eyes, which are more susceptible to nonlinear interference. Only a stronger DFE can adjust all three "small eyes" to be clear, ensuring the signal can be received normally.

5. Signal Integrity: Stricter Requirements, No Room for Compromise

It’s clear from the parameter table above that PCIe 6.0’s testing requirements are much stricter than 5.0’s. Let’s break down exactly how strict they are, one by one:

- Rx Test Eye Height: Reduced from 15mV in 5.0 to 6mV in 6.0 (only for the top eye), which is equivalent to more than doubling the "clarity standard" for signals.

- Rx Test Eye Width: Reduced from 9.375ps in 5.0 to 3.125ps in 6.0 (still for the top eye), which also greatly increases the requirement for time accuracy.

- Reference Clock Jitter Requirement: Tightened from ≤0.25ps RMS to ≤0.15ps RMS. Simply put, the clock stability requirement is higher, with no room for deviation.

- Channel Loss Budget: Reduced from 36dB @16GHz to 32dB @16GHz, meaning the signal attenuation during transmission cannot be too large, and the hardware requirements are more stringent.

This means that designs that were "good enough" in the PCIe 5.0 era will be completely useless in the 6.0 era. Every hole on the PCB, every millimeter of wiring, and every connector must be precisely controlled—no room for carelessness.

There are several key challenges here, which I’ll highlight for everyone:

1.  PCB Material: Must use ultra-low loss materials, such as MEGTRON 7 and RO4835. Ordinary FR-4 materials we usually use can’t withstand signal attenuation at 32GHz and will easily cause data transmission errors if used.

2.  Connectors: Surface-mount connectors have become standard, and the press-fit process must be extremely precise. A slight deviation will affect the signal and cause unstable transmission.

3.  Power Supply Stability: PAM4 is very sensitive to power supply interference. The previous power supply design can’t meet the requirements at all, so the power distribution network (PDN) must be redesigned to ensure stable power supply.

4.  Crosstalk Control: The spacing of differential pairs, the vias of shielded ground—every detail can’t be omitted. A slight oversight will cause crosstalk between signals and affect transmission quality.

6. Commercial Prospects: Enterprise-Grade First, Consumer-Grade to Wait

From a practical application perspective, the positioning of these two generations of products is very different. Let’s break it down into two categories, so everyone can understand at a glance.

PCIe 5.0 is now fully popular in AI servers and data centers. Whether it’s NVIDIA’s RTX 50 series graphics cards, AMD’s RX 9000 series graphics cards, or enterprise-grade solid-state drives (SSDs), all support PCIe 5.0 and are widely used.

In contrast, the commercialization of PCIe 6.0 is relatively slow. Although the specification was released in early 2022, actual available devices won’t hit the market until 2026. There are three main realistic reasons for this:

1.  High Cost: The tape-out cost of a PCIe 6.0 controller is about 20-35 million US dollars, twice that of 5.0. Manufacturers have high investment costs and won’t easily put it into mass production.

2.  High Technical Threshold: PAM4 design, product verification, and testing all require a brand-new toolchain. Many manufacturers haven’t mastered this technology yet and can’t produce qualified products in a short time.

3.  Divergent Demands: AI and high-performance computing (HPC) data centers really need the high bandwidth of PCIe 6.0 for faster data transmission and higher efficiency. However, for ordinary consumer computers and game consoles, there’s almost no demand for 6.0—current PCIe 5.0 SSDs are already so fast that users can’t perceive the difference; faster speeds are unnecessary.

According to industry forecasts, PCIe 6.0 may not be popular in the consumer market until after 2030. But in the enterprise-grade field, especially AI servers, large-scale deployment will begin in 2026-2027, first landing in professional fields.

Summary: The Essential Difference Between the Two Generations

Back to the original question: What’s the real difference between PCIe 5.0 and 6.0?

To sum it up in plain language: 5.0 is the ceiling of the NRZ encoding era, pushing old technology to its limit; while 6.0 is the starting point of the PAM4 encoding era, opening up a brand-new technical route.

For engineers, working on PCIe 5.0 tests their ability to refine and perfect old technologies; working on PCIe 6.0 tests their ability to learn new technologies and adapt to new routes. For the entire industry, 5.0 is a mature technology that is usable and reliable today, while 6.0 is the future direction—but this future will first come from data centers, then slowly make its way into the lives of ordinary users.

|（注：文档部分内容可能由 AI 生成）